1. Field of the Invention
The present invention is related to power semiconductor device, more particularly, to output transistor protection in power semiconductor devices.
2. Description of the Related Art
In automobiles and home electric appliances, power semiconductor devices (also called power devices or power ICs) are often used for high-current and/or high-voltage power control. Common power semiconductor devices are provided with function for protection of the output transistor from the overcurrent, which may result from circuit failure, such as short-circuiting of the load.
Japanese Laid-Open Patent Application No. 2001-160746 (hereinafter, referred to as the '746 application) discloses a power semiconductor device 101 adapted to output transistor protection, the configuration of which is illustrated in FIG. 1. The power semiconductor device 101 is provided with a power supply terminal Vcc, a ground terminal GND, an input terminal IN, and an output terminal OUT. The ground terminal GND is earth-grounded. The power supply terminal Vcc is connected to a positive electrode of a battery 111, and a negative electrode of the battery 111 is earth-grounded. The output terminal OUT is connected to one end of a load 112 and the other end of the load 112 is earth-grounded.
The power semiconductor device 101 functions as a high-side switch, connected between the load 112 and the battery 111. The power semiconductor device 101 is provided with a control circuit 102 and a switch M100 used to control the electric current through the load 112. The switch M100 is comprised of an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and therefore the switch M100 is referred to as an output MOS transistor M100, hereinafter. The output MOS transistor M100 has a drain connected to the power supply terminal, and a source connected to the output terminal OUT.
The control circuit 102 includes a charge pump circuit 103. The charge pump circuit 103 is connected to the input terminal IN on the input thereof, and connects to the gate G101 of the output MOS transistor M100 on the output thereof. The charge pump circuit 103 is connected to the power supply terminal Vcc, receiving a power supply voltage from the battery 111. The charge pump circuit 103 provides the gate voltage the output MOS transistor M100 on the gate G101 in response to a control signal received from the input terminal IN, and the output MOS transistor M100 controls the current through the load 112 in response to the gate voltage thereof.
When the control signal fed to the input signal IN is deactivated, the charge pump circuit 103 pulls down the gate voltage of the output MOS transistor M100 to the low level, to thereby turn off the output MOS transistor M100. When the control signal is activated, on the other hand, the charge pump circuit 103 pulls up the gate voltage of the output MOS transistor M100 to the high level to turn on the output MOS transistor M100. In other words, the charge pump circuit 103 boosts the power supply voltage fed from the battery 111 in response to the activation of the control signal, and outputs the boosted electric voltage to the gate G100 of the output MOS transistor M100. The output MOS transistor M100 is turned on in response to the activation of the gate voltage thereof up to the boosted power supply voltage.
It should be noted that the short-circuiting of the load 112 mentioned above means undesired electrical connection bypassing the load 112 between the output terminal OUT and the ground terminal GND; this may be caused by detachment of an insulation film and loosening of a connector, for example. When short-circuiting of the load 112 occurs, the voltage level on the power supply terminal Vcc drops to near 0V or the ground level. This is because the voltage drop mainly occurs across the power wire line between the battery 111 and the power semiconductor device 101, when the short circuiting of the load 112 occurs; the impedance of the power wire line between the battery 111 and the power semiconductor device 101 is usually much higher than the on-resistance of the output MOS transistor M100 (typically, several mΩ or several-tens of mΩ), especially when the power wire line is long (see FIG. 5A). Short-circuiting of the load 112 also causes an unacceptable increase in the output current Iout. When the current intensity of the output current Iout exceeds an allowable level, the output MOS transistor M100 may experience thermal destruction caused by the excessively large output current Iout. The output MOS transistor M100 must be off as soon as possible, when the load 112 is short-circuited.
In order to achieve protection of the output MOS transistor M100, the control circuit 102 further includes an overcurrent protection circuit 104. The power supply voltage supplied from the battery 111 to the power supply terminal Vcc is higher than the operation voltage of the overcurrent protection circuit 104.
The overcurrent protection circuit 104 monitors the output current Iout of the output MOS transistor M100. When an overcurrent event occurs for the output current Iout, the overcurrent protection circuit 104 detects the overcurrent event, determining that the current level of the output current Iout exceeds a given reference level, for example. The overcurrent protection circuit 104 then outputs an output shutoff signal to the charge pump circuit 103, and provides an electrical connection between the gate G101 of the output MOS transistor M100 and the ground terminal GND. In response to the output shutoff signal, the charge pump circuit 103 stops providing the gate voltage to the output MOS transistor M100. In addition, the overcurrent protection circuit 104 discharges electric charges accumulated on the gate G101 of the output MOS transistor M100 and thereby turn off the output MOS transistor M100. Such operation effectively provides protection of the output MOS transistor M100 from overcurrent.
The overcurrent protection circuit 104 includes a monitor circuit 105 and the overcurrent protection MOS transistor M101. The overcurrent protection MOS transistor M101 is an N channel MOSFET having a drain connected to the gate G101 of the output MOS transistor M100, and a source connected to the ground terminal GND. The monitor circuit 105 is connected between the power supply terminal Vcc and the ground terminal GND. The monitor circuit 105 is further connected to the gate of the overcurrent protection MOS transistor M101 on the output thereof.
The monitor circuit 105 effectively avoids the overcurrent destruction of the output MOS transistor M100 by monitoring the output current Iout of the output MOS transistor M100 and providing the gate voltage of the overcurrent protection MOS transistor M101 in response to the monitored output current Iout.
For example, when the current level of the output current Iout does not exceed a specific reference level, the monitor circuit 105 deactivates the gate voltage of the overcurrent protection MOS transistor M101 to turn off the overcurrent protection MOS transistor M101. When determining that the current level of the output current Iout exceeds the reference level, the monitor circuit 105 detects the occurrence of the overcurrent event, and pull up the gate voltage of the over current protection MOS transistor M101 to thereby turn on the overcurrent protection MOS transistor M101. The turn-on of the overcurrent protection MOS transistor M101 effectively avoids the overcurrent destruction of the output MOS transistor M100, allowing the discharge of the electric charges on the gate G101 of the output MOS transistor M100 to the ground terminal GND to thereby turn off the output MOS transistor M100 off.
As discussed in the '746 application, the source of the overcurrent protection MOS transistor M101 may be connected to the output terminal OUT instead of the ground terminal GND as shown in FIG. 2; such modified power semiconductor device is denoted by the numeral 101′ in FIG. 2. When short-circuiting of the load 112 occurs, the power semiconductor device 101′ operates similarly to the power semiconductor device 101.
Japanese Laid-Open Patent Application No. JP-A 2006-86507 discloses a modified configuration of the power semiconductor device, which is illustrated in FIG. 3. In FIG. 3, the modified power semiconductor device is denoted by the numeral 101″. In the power semiconductor device 101″, the overcurrent protection circuit 104 additionally includes a monitor circuit 106. The monitor circuit 106 is connected to the power supply terminal Vcc and is connected to the ground terminal GND. In addition, the monitor circuit 106 is connected to the backgate of the overcurrent protection MOS transistor M101 on the output thereof.
The monitor circuit 106 effectively avoids the overcurrent destruction of the output MOS transistor M100 by monitoring the output current Iout of the output MOS transistor M100 and controlling the backgate voltage of the overcurrent protection MOS transistor M101. The monitor circuit 106 controls the backgate voltage of the overcurrent protection MOS transistor M101 to achieve on-and-off control of the parasitic bipolar transistor of the overcurrent protection MOS transistor M101.
Specifically, when the current level of the output current Iout does not exceed a specific reference level, the monitor circuit 106 controls the level of the backgate voltage of the overcurrent protection MOS transistor M101 to the low level to place the overcurrent protection MOS transistor M101 into the off-state. When the overcurrent event occurs, the monitor circuit 106 detects the occurrence of the overcurrent event, determining that the current level of the output current Iout exceeds the reference level, and pulls up the level of the backgate voltage of the overcurrent protection MOS transistor M101 to turn on the parasitic bipolar transistor of the overcurrent protection MOS transistor M101. The turn-on of the overcurrent protection MOS transistor M101 effectively avoids the overcurrent destruction of the output MOS transistor M100 by discharging electric charges accumulated on the gate G101 of the output MOS transistor M100 to the ground terminal GND, and placing the output MOS transistor M100 into the off state.
Differently from the monitor circuit 105, the monitor circuit 106 is designed to operate on an operation voltage lower than that of the monitor circuit 105. For example, as shown in FIG. 4A, the monitor circuit 106 is provided with a resistance element R1 and an overcurrent protection MOS transistor M102, which are connected in series between the power supply terminal Vcc and the ground terminal GND. The resistance element R1 is connected to the power supply terminal Vcc at one end thereof. The overcurrent protection MOS transistor M102 is an N-channel MOSFET that has a drain connected to another end of the resistance element R1, a gate connected to the power supply terminal Vcc, and a source connected to the ground terminal GND. The backgate of the overcurrent protection MOS transistor M101 is connected to a connection node N101 between the resistance element R1 and the overcurrent protection MOS transistor M102.
Such configuration of the monitor circuit 106 allows operating the parasitic bipolar transistor, denoted by the numeral Tr101 in FIG. 4B, within the overcurrent protection MOS transistor M101. FIG. 4B illustrates an exemplary section structure of the overcurrent protection MOS transistor M101. A P-well region 120 is formed within the surface portion of a semiconductor substrate. A gate electrode 121 is formed over the P-well region 120 as the gate of the overcurrent protection MOS transistor M101. Within the surface portion of the P-well region 120, N+ drain and source regions 122 and 123 are formed across the gate electrode 121 as a drain and source of the overcurrent protection MOS transistor M101, respectively. A P+ backgate contact region 124 is additionally formed within the surface portion of the P-well region 120, positioned away from the source region 123. The backgate contact region 124 is connected to the node N101. The parasitic bipolar transistor Tr101 operates as an NPN bipolar transistor composed of the N+ source region 123, the P-well region 120, and the N+ drain region 122. As shown in FIGS. 4B and 4C, the drain, the source, and the backgate of the overcurrent protection MOS transistor M101 functions as the collector, the emitter, and the base of the parasitic bipolar transistor Tr101, respectively. This implies that the parasitic bipolar transistor Tr101 is connected to the gate G101 of the output MOS transistor M100 at the collector thereof, connected to the ground terminal GND at the emitter thereof, and connected to the node N101 at the base thereof.
The parasitic bipolar transistor Tr101 effectively discharges electric charges in the gate G101 of the output MOS transistor M100 to the ground terminal GND, when an overcurrent flows through the output MOS transistor M100, even when the voltage level on the power supply terminal Vcc is low. In detail, the parasitic bipolar transistor Tr101 is turned on to provide the electrical connection between the collector and the emitter, allowing the discharge of the electric charges on the gate G101, when the node N101 has a voltage level exceeding the turn-on base-emitter voltage (the base-emitter voltage at which the parasitic bipolar transistor Tr101 is turned on), feeding a base current to the parasitic bipolar transistor Tr101.
The turn-on voltage of the parasitic bipolar transistor Tr101 is lower than the threshold voltages of the overcurrent protection MOS transistors M101 and M102 and the operation voltage of the monitor circuit 105, on which the monitor circuit 105 can detect the overcurrent event. The turn-on voltage of the parasitic bipolar transistor Tr101 is typically 0.6 V. Generally, it is hard to integrate a MOS transistor with a low threshold voltage within a power semiconductor device, because MOS transistors integrated within a power semiconductor device requires a thick gate dielectric for handling high voltage. The power semiconductor device 101″ addresses achieving low voltage operation by making use of the parasitic bipolar transistor operation, instead of the MOS transistor operation. That is to say, the monitor circuit 106 can operate on an operation voltage lower than that of the monitor circuit 105. This effectively allows the monitor circuit 106 to detect the overcurrent event, before the monitor circuit 105 is activated to detect the overcurrent event.
The above-described power semiconductor device 101, 101′ and 101″, however, does not provide overcurrent protection for the output MOS transistor M100, when the voltage level of the power supply terminal Vcc is extremely low, as low as the ground level (or 0V), for example.
Referring to FIGS. 5A and 5B, let us consider a case in which short-circuiting occurs for the load 112 connected to the power semiconductor device 101 or 101′. In this case, the overcurrent protection circuit 104 cannot operate as desired, when the voltage level on the power supply terminal Vcc is excessively lowered, as low as the ground level, for example. When the voltage level on the power supply terminal Vcc is lower than the allowed minimum operation voltage of the monitor circuit 105, for example, the monitor circuit 105 cannot determine whether the current level of the output current Iout of the output MOS transistor M100 exceeds the reference level. In addition, when the voltage level on the power supply terminal Vcc is less than the threshold voltage of the overcurrent protection MOS transistor M101, the overcurrent protection MOS transistor M101 is never turned on. This undesirably hinders the power semiconductor devices 101 and 101′ from discharging electric charges on the gate G101 of the output MOS transistor M100 to the ground terminal GND, when the overcurrent event occurs. Therefore, the output MOS transistor M100 may experience thermal destruction when the overcurrent event is continued with the output MOS transistor M100 kept turned off.
This drawback is not overcome by the power semiconductor device 101″ shown in FIG. 3. Let us consider a case in which short-circuiting occurs for the load 112 connected to the power semiconductor device 101″ as shown in FIGS. 5A and 5B. The overcurrent protection circuit 104 cannot normally operate neither, when the voltage level on the power supply terminal Vcc is extremely lowered, as low as the ground voltage or 0V. When the voltage level on the power supply terminal Vcc is less than the allowed operation voltage of the monitor circuit 105, for example, the monitor circuit 105 cannot determine whether the current level of the output current Iout of the output MOS transistor M100 exceeds the reference level. In addition, when the voltage level on the power supply terminal Vcc is less than the threshold voltage of the overcurrent protection MOS transistor M101, the overcurrent protection MOS transistor M101 is never turned on. Furthermore, when the voltage level on the power supply terminal Vcc is lower than the turn-on voltage of the parasitic bipolar transistor Tr101 in the monitor circuit 106 (typically, 0.6V), that is, when the voltage level on the node N101 is lower than the turn-on base-emitter voltage of the parasitic bipolar transistor Tr101, prohibiting the base current from being fed to the parasitic bipolar transistor Tr101, electric charges on the gate G101 of the output MOS transistor M100 are not discharged with the parasitic bipolar transistor Tr101 turned off. As a result, the conventional power semiconductor device 101″ does not discharge electric charges on the gate G101 of the output MOS transistor M100 to the ground terminal GND when the overcurrent event occurs. The output MOS transistor M100 may experience thermal destruction, when the overcurrent event is continued thereafter with the output MOS transistor M100 kept turned off.